1. Field of the Invention
The present invention relates to an active matrix type display device, and more particularly to a pixel memory system liquid crystal display device and an electroluminescence type display device exhibiting high numerical aperture and high definition.
2. Description of the Related Art
Liquid crystal display devices have been widely adopted as display devices which can perform a color display of high definition for note-type computers and display monitors.
As such liquid crystal display devices, simple matrix type liquid crystal display devices each of which adopts a liquid crystal display element which sandwiches a liquid crystal layer with a pair of substrates which form parallel electrodes arranged in an intersecting manner on respective inner surfaces and active matrix type liquid crystal display devices each of which adopts a liquid crystal display element having switching elements for selecting per pixel on one of a pair of substrates have been known.
A thin film transistor (TFT) type liquid crystal display device which is a typical example of the active matrix type liquid crystal display device applies signal voltages (video signal voltage: gray scale voltage) to a pixel electrode using a thin film transistor TFT provided to each pixel as a switching element and hence, there is no crosstalk between pixels so that the multi-gray scale display having high definition can be realized.
On the other hand, when this type of liquid crystal display device is mounted on an electronic device such as a portable type information terminal or the like which uses a battery as a power source, the reduction of the consumed power which is initiated by the display becomes necessary. To that end, many proposals have been made conventionally with respect to ideas to make each pixel of the liquid crystal display device have a memory function.
FIG. 14 is an explanatory view showing an example of the constitution of one pixel of a liquid crystal display device which makes each pixel have a memory function. FIG. 14 shows a so-called dynamic memory type, wherein a memory capacitor is provided to an output side (pixel electrode side) of a thin film transistor TFT mounted on a point of intersection between a signal line and a scanning line and display data is held for a given time after inputting the display data into the memory capacitor. In the drawing LC indicates a liquid crystal capacitor.
This dynamic memory type has to be refreshed periodically since the data held in the memory capacity leaks as time elapses. Particularly, when the memory function of the pixel is constituted using the polycrystalline silicon semiconductor, there is a tendency that the leak current is increased. Accordingly, it is necessary to shorten the refreshing cycle.
However, when the refreshing cycle is shortened, it brings about a drawback that an advantageous effect that the unnecessary writing can be omitted by giving the memory function to each pixel so that peripheral circuits and the power consumption can be reduced is decreased.
To solve the above-mentioned drawback, an active matrix type display device which adopts a static memory type in place of the dynamic memory type has been proposed.
FIG. 15 is an essential part circuit diagram for explaining an example of memory circuit of a static memory type described in FIG. 3 of Japanese Laid-open Patent Publication 333094/1992. In the drawing, a portion surrounded by a chained line indicates a pixel memory. This circuit is comprised of a NMOS transistor 111, a PMOS transistor 112 and inverters 121, 122. Scanning signals Vg are supplied to gates of the NMOS transistor 111 and the PMOS transistor 112, while gray scale signals (brightness signals) Vd are supplied to a drain of the NMOS transistor 111. A source of the NMOS transistor 111 is connected to an input of the inverter 122 together with a source of the PMOS transistor 112.
An output DM of the memory circuit which selects the liquid crystal drive voltage is taken out from an output of the inverter 122. The inverter 121 receives this signal DM as an input and an output of the inverter 121 is connected to a drain of the PMOS transistor 112.
The NMOS transistor 111 takes the “OFF” state when the scanning signal Vg is set to “0” and becomes the “ON” state when the scanning signal Vg is set to “1”. To the contrary, the PMOS transistor 112 becomes the “OFF” state when the scanning signal Vg is set to “1” and becomes the “ON” state when the scanning signal Vg is set to “0”. Accordingly, the memory circuit interrupts the brightness signal Vd when the scanning signal Vg is set to “0” and connects the output of the inverter 121 to the input of the inverter 122 so that data storage state is obtained. Further, when the scanning signal Vg is set to “1”, the memory circuit connects the brightness signal Vd to the input of the inverter 122 so as to obtain the data passing state.
FIG. 16 is an essential part circuit diagram for explaining another example of a memory circuit of a static memory type described in FIG. 2(b) of Japanese Laid-open Patent Publication 194205/1996. In the drawings, a portion surrounded by a chained line indicates a pixel memory. This circuit is comprised of switching elements 21, 22, 23 and 24 which are formed of thin film transistors arranged at intersecting portions between scanning lines 3 and signal lines 4. The switching elements 22, 23 constitute an inverter and forms a memory circuit. A scanning voltage (pulse) is applied to the scanning line 3 and, in synchronism with this step, a signal which controls the opening/closing of the switching element 24 is inputted to the switching element 21 though the signal line 4.
As other prior art which provides a memory to each pixel, there have been known techniques disclosed in Japanese Laid-open Patent Publication 102530/1994, Japanese Laid-open Patent Publication 286170/1996, Japanese Laid-open Patent Publication 113867/1997, Japanese Laid-open Patent Publication 212140/1997, Japanese Laid-open Patent Publication 65489/1997 and Japanese Laid-open Patent Publication 75144/1999.
However, in any one of these prior arts, a DC voltage whose voltage level is not changed is applied to a power supply node of a memory circuit of each pixel every hour and hence, a technical concept to apply an AC voltage whose voltage level is changed along with the lapse of time to a power supply node of a memory circuit has been neither disclosed nor suggested in these prior arts.
Accordingly, in any one of these prior arts, it is necessary to particularly provide wiring for supplying a DC current for each pixel to maintain the storage of memory of each pixel.
In the above-mentioned conventional constitution, since the liquid crystal display device adopts the static memory type, it is necessary to supply two fixed voltages to each pixel, that is, high and low voltages which are originally unnecessary in a pixel array portion of the liquid crystal display device and hence, particular wiring for such fixed voltages becomes necessary and this leads to the lowering of the numerical aperture particularly in the transmission type liquid crystal display device.
Further, not to mention with respect to the transmission type liquid crystal display device, even in the reflection type liquid crystal display device and the electroluminescence display device, wiring of peripheral circuits such as drivers which drive pixels becomes large in number so that the peripheral region of the display device becomes large thus interrupting the miniaturization of the liquid crystal display device.